Bad Pins

Yes, it is certainly possible that there is something wrong with the board. But I have already verified about half of the functionality of this FPGA design. These test pins are only routed directly to Test-points on the board. (They are not connected to multiple places.)

Also I have had correct signals on these test pins earlier. Then several pins stopped working. Since I didn't know I could delete the db folder, I created a new design and re-drew the TOP block. I thought that had fixed the problem.

I am currently looking at the Technology Map Viewer, and all pins are shown correctly.

Thanks for your continued assistance.

John

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Thanks to both of you for your suggestions. I will try them today.

I certainly don't expect that it would be a problem with Quartus, but it seems so strange. I worked with Quartus quite a bit about a year ago and never had any problems like this.

It is a new board. All the pins are assigned correctly.

Again thank you.

John

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Hi John,

is it possible that the board itself is the problem ?

An easy way to check what Quartus did with your design is to look into the RTL or Technology View.

Kind regards

GPK

Thanks to both of you for your suggestions. I will try them today.

I certainly don't expect that it would be a problem with Quartus, but it seems so strange. I worked with Quartus quite a bit about a year ago and never had any problems like this.

It is a new board. All the pins are assigned correctly.

Again thank you.

John

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I am a rookie. I am working on my fourth MAX II design. I am using Quartus II Version 9 SP2.

The problem I am having is that several pins on EPM1270 do not work. For example. I have four test pins I use for debugging. If I connect the clock to all four of these pins (set up as outputs), the oscillator signal only comes out of one of the four test pins. (There are probably other pins that are not working, but I haven't found them yet.)

This seems like a Quartus problem to me. I would appreciate any advice. Especially, is there a file that I can delete that will ensure a complete re-build?

Thank you for any constructive suggestions.

John

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Hi John,

there a lot of possibilties why your design isn't working.

1. Your board or your MAX devcie is broken

Is it a new board or did you have run a design on it in the past ?

Can you assign your output to other pins ?

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2. Your design

Did you check that the clock is really connected to the outputs ?

Use the Quartus Tech View for checking.

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3. Quartus

Did you check your pin assignment ? Are the output assigned ??

One way to force Quartus to re-build the database is to delete the db folder.

Kind regards

GPK

Generally, deleting the db directory resets all previous compilation results.

Although there's always a possibility of revealing new Quartus bugs, your obervation sounds somewhat unlikely in my opinion. You didn't tell about your design implementation method, but you have the option to check the Place&Route result in the Technology Map Viewer.