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Altera_Forum's avatar
Altera_Forum
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9 years ago

avalon streaming pipeline and ready cycles

Hello,

Good day! hope you are all doing great!! :)

I have a problem of creating avalon streaming component. Building piplelined delayed component that has both source and sink ports and support backpressure to deal with TSE ip core.

In order to do that I created a VHDL file and created a new component in QSys, define the st signals such as data, valid, ready, startofpacket and endofpacket signals for input and output.

I looked into qsys avst delay but unfortunetly it doesnt support backpressure. Do I need to add Timing Adapters before and after my avst component pipelined stages, if so and how to do that?

In the code, I check if the in_valid signal is asserted and then just pass the data, startofpacket and endofpacket signals through pipelined stages(N stages). what i notice is tha packets flow correctly with lower burst chunks, but when I have large burst, it starts to lose some portion of packets or overwrite others. So, I believe there's something I miss with dealing with ready signal and ready latency as well.

What I want to do in clear words is to have a core between two streaming cores as Qsys streaming Delay Stage that receive streamed data from sink port, process it and send it to the source port. and that processing takes some clocks that why I need it pipelined.

Thank you in advance. it would be greatly appreciated

Kind regards,

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hello Ghazis,

    As long as you follow the avalon st specifications (google avalon specifications), qsys will make sure the timing is correct between the interfaces. The parameters entered when creating the component is what qsys uses to meet the synchronization. If those are wrong, you will have problems. Overall, you dont need to pipeline since it does it for you

    --Trukng
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hello Trukng,

    Thank you for your response i really appreciate that.

    I'm assuming then that readylatency = 0, so whenever i found in_ready='1' and in_valid='1' i catch the the in_data and all other streaming signals such as sop,eop,error, empty.

    it works really fine and the stream flows correctly when i just wire the signals to the output. But what i did is to pass them through pipelined registers let say 10 clock cycles. and the output of the tenth registers is wired with the output (out_data <= in_data_reg10; -- same for other avalon st signals). in this case, i found the problems.

    i believe it is due to the ready handshaking between source and the sink ports my component that's why I tried to put SCFIFO in the avalon st source ports of my component to handle the handshaking, but unfortunately the same behavior. packets at some point get a portion loss.

    regards,

    --ghazis.