avalon streaming pipeline and ready cycles

Hello Trukng,

Thank you for your response i really appreciate that.

I'm assuming then that readylatency = 0, so whenever i found in_ready='1' and in_valid='1' i catch the the in_data and all other streaming signals such as sop,eop,error, empty.

it works really fine and the stream flows correctly when i just wire the signals to the output. But what i did is to pass them through pipelined registers let say 10 clock cycles. and the output of the tenth registers is wired with the output (out_data <= in_data_reg10; -- same for other avalon st signals). in this case, i found the problems.

i believe it is due to the ready handshaking between source and the sink ports my component that's why I tried to put SCFIFO in the avalon st source ports of my component to handle the handshaking, but unfortunately the same behavior. packets at some point get a portion loss.

regards,

--ghazis.