Avalon mm pipeline bridge problem: multible write

You don't specify in your HDL what irq_en should be when write is low, so you've basically created a latch.

But I don't understand why in your Signal Tap capture writedata[1] does not match what is shown for writedata[7..0]. Are you sure you are tapping the correct signals or accidentally tapping a different writedata[1]?

assign irq_signal = irq_en & reset_assert;

always @(posedge clk or negedge reset_n)
begin
     if (reset_n == 1'b0)
          irq_en <= 1'b0;
     else if (write)
          if (writedata[0])
               irq_en <= 1'b1;
          else
               irq_en <= 1'b0;

Your "write" signal is essentially a synchronous clock enable for the register and writedata[0] is a synchronous set. You just have to cover both cases for it. This should now synthesize correctly.