Contributor
ContributorHi
irq_en is what I want to have,
reset_wr signal is not, I didnt expect 4 write signal when using alt_write_byte().
And yes, they are the same signal, which makes this case stranger.
Super ContributorYou do not want to have a latch, especially in an FPGA design. They make it difficult to meet timing and can cause glitching. That could be part of this problem depending on how irq_en is working with the rest of the design.
As for the weird writedata, I'd try removing and re-adding the signals in the .stp file or just create a brand new .stp in case the file is corrupt.
ContributorThank you,
I'd have a try.
ContributorHi，Sstrell
Since you mentioned on the latch problem,
do you mind sharing how you handle level-sensitive registers?
what Im trying to do is that irq_signal = irq_en & reset_assert.
irq_en should always be 1(if I write 1) until I write 0.
Thank you very much
