Forum Discussion
Autostart NIOS from external SDRAM problem
So my NIOS code has outgrown the available on chip RAM and I've moved it to off chip SDRAM. Very slow, but I fire up Eclipse and I can get it to run. I need to get it to run automatically and I've found snippets of information by perusing the NIOSII software developers Handbook but can anyone point me to definitive documentation. I know I need to persuade the compiler to produce a ROM image that becomes a MIF, which I believe it does, and get something (maybe a bootloader) to do the initialisation, and somewhere I need to tell the tools to run that code.
Can anyone help with the blanks?
36 Replies
- EBERLAZARE_I_Intel
Regular Contributor
Hi,
Please check this page, and let me know which method would you like to go for?:
- Oliver_I_Sedlacek
Contributor
Aha, so I was looking in the wrong manual!
Well I've chewed my way through the instructions and as I expected my NIOS neither runs nor can I debug it from Eclipse. The manual does not list any steps for diagnosing faults, so where do I go from here?
- EBERLAZARE_I_Intel
Regular Contributor
Hi,
Apologies I came back a bit late, for debugging it is on chapter 6.
- Oliver_I_Sedlacek
Contributor
I've read chapter 6 and none of it really sheds any light on my problem. My system runs perfectly and the code has been debugged, so I suspect vector offsets are broken but I don't know how to inspect them if I can't connect the debugger.
- EBERLAZARE_I_Intel
Regular Contributor
Hi,
Could you provide your design example? Or is your example similar to any of the booting methods in the Embedded Handbook?
- Oliver_I_Sedlacek
Contributor
The intent was to go with application code stored in EPCQ flash and the run time location is external RAM as per Table 33 and section 5.2.3.4 of the Embedded Design handbook. The SOF is 802 kB in size so I just rounded up to make the offset to the HEX 1024 kB.
As I stated earlier, everything works if I load the application from the Eclipse debugger, but I do need it to run from power up.
I've added a project archive, all done in Quartus 20.1 Lite.
- EBERLAZARE_I_Intel
Regular Contributor
Hi,
I think I got it what you intend to do, let me work on it and get back to you.
- Oliver_I_Sedlacek
Contributor
Thanks
- EBERLAZARE_I_Intel
Regular Contributor
Hi,
You could do the programming using .jic:
https://www.intel.com/content/www/us/en/docs/programmable/683689/current/programming-96050.html
With programming using .jic, you can reset your FPGA device using the reset button or power cycle your hardware and it will run upon power up. Is this what you are trying to achieve?
- Oliver_I_Sedlacek
Contributor
The FPGA configures fine from power up (programmed via .JIC as suggested). The problem is the NIOS doesn't boot. I've been following Table 33 and section 5.2.3.4 of the Embedded Design handbook but I'm obviously doing something wrong, but can't diagnose what.
- EBERLAZARE_I_Intel
Regular Contributor
Hi,
I cannot find any major differences in your design. Have you tried to use the example in the document and start from there? :