Forum Discussion
New ContributorAssistance Required: Persistent Oscillation Issues on MAX10 LVDS Receiver Inputs
Hi,
I believe the answer is implementation dependent. Adding a DC bias to enforce a 0 or 1 level for floating LVDS inputs would reduce performance, e.g. increase minimal signal level and add an asymmetrical time shift of input signal, reducing effective skew margin. Both effects reduce maximal cable length. Common mode bias is required in AC coupled input circuit, but differential bias is rarely applicable for high speed differential signaling.
When receiving an open LVDS input signal with 10b8b decoder, we still get a certain rate of false correct frames. An additional time filter detects stable input signal.
Super ContributorHi,
the problem description is pretty clear, I think. There's however no general solution, it has to be taylored to your system.
As already stated, there's no fail-safe feature for LVDS receivers. For relative low speed of 80 MSPS, dc bias to a defined idle state (LVDS as such has no defined idle state) can be a solution. If communication time budget allows, a longer preamble can also help.
Regards
Frank
