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New ContributorAssistance Required: Persistent Oscillation Issues on MAX10 LVDS Receiver Inputs
Hi,
I believe the answer is implementation dependent. Adding a DC bias to enforce a 0 or 1 level for floating LVDS inputs would reduce performance, e.g. increase minimal signal level and add an asymmetrical time shift of input signal, reducing effective skew margin. Both effects reduce maximal cable length. Common mode bias is required in AC coupled input circuit, but differential bias is rarely applicable for high speed differential signaling.
When receiving an open LVDS input signal with 10b8b decoder, we still get a certain rate of false correct frames. An additional time filter detects stable input signal.
New ContributorThank you for your follow-up.
I have configured the interface as a bidirectional LVDS bus operating at 80 MHz. To support this, the design includes termination resistors at both ends of the bus for proper signal integrity.
As for the oscillation observed:
It manifests as white noise-like behavior on the LVDS receiver inputs. Importantly, this oscillation only occurs before the LVDS driver becomes active—specifically, during the idle state prior to any valid signal transmission.
The protocol implemented includes a synchronization code at the start of each packet, and the receiver performs multiple checks to detect it. However, due to the random timing introduced by this pre-driver oscillation, the sync code is often missed or misaligned, affecting packet recognition and initial link stability.
Please let me know if any further clarification is needed. I would appreciate any guidance or recommendations to mitigate this behavior.
Best regards, Sung-jin
