Hi,
I'm not aware of a any kind of fail-safe mechanism specified for LVDS inputs of Altera FPGA neither MAX10 nor other types.
MAX10 Table 25. Differential I/O Standards Specifications for Intel MAX 10 Devices specifies a minimal differential voltage Vid of 100 mV and a common mode range. Receiver state for Vid between +/- 100 mV is undefined.
According to TIA PN-4584, failsafe operation means are optional and not covered by the standard:
4.4.2 Failsafe operation
Other standards and specifications using the electrical characteristics of the LVDS interface circuit may require that specific interchange circuits be made failsafe to certain fault conditions. Such fault conditions may include one or more of the following:
1) generator in power-off condition
2) receiver not connected with the generator
3) open-circuited interconnecting cable
4) short-circuited interconnecting cable
5) input signal to the load remaining within the transition region (±100 mV) for an abnormal period of time (application dependent)
When detection of one or more of the above fault conditions is required by specified applications, additional provisions are required in the load and the following items must be determined and specified:
1) which interchange circuits require fault detection
2) what faults must be detected
3) what action must be taken when a fault is detected; the binary state that the receiver assumes
4) what is done does not violate this Standard
The method of detection of fault conditions is application dependent and is therefore not further specified as it is beyond the scope of this Standard.
Please correct me if you know different specifications for Altera FPGA.
Fail safe behaviour is implemented with some RS485 receivers on the market, but it typically doesn't work for terminated inputs. In case of LVDS, we usually implement detection of floating/unconnected inputs on higher protocol levels.
Regards
Frank
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