fst21
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New ContributorAssignment RTL_PARAMETER
Hello,
I use the PLL Reconfig Intel FPGA IP core for Arria 10, which uses one fifo each for data and command synchronization. These fifos are mapped as block RAM in M20K despite the small size of only 144 bits. My goal is to use MLAB memory for this.
Unfortunately, with Quartus 22.3 the ram_block_type parameter of the sc_fifos is not passed to the toplevel of the PLL Reconfig IP, so that a change via a QSF assignment seems to be the most sensible way.
The following assignment was not successful although the assignment editor recognizes this as correct and Quartus does not issue an error message or warning:
set_instance_assignment -name RTL_PARAMETER "ram_block_type=\"MLAB\"" -to gen_AccSocketPLL[0].inst_SocketPLLReconfig|pll_reconfig_0|reconfig.reconfig_core.iopll_reconfig_core_inst|command_fifo|scfifo_component -entity NallatechA10385A_HWFramework
Does anyone have any idea how the assignment has to be formulated correctly? Or how the goal can be achieved with a different method?
Thanks you very much,
Fritjof
As it turns out, there's no way to change it other than changing the Verilog code.
Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.
Regards,
Richard Tan
