Forum Discussion
New ContributorAssignment RTL_PARAMETER
As it turns out, there's no way to change it other than changing the Verilog code.
Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.
Regards,
Richard Tan
8 Replies
- RichardT_altera
Super Contributor
RTL_parameter is mostly used for PR design flow. I don't think it is applicable in this case.
Reference:
For generated IP, one way that I can think of is to add the RAM_BLOCK_TYPE defparam in the fifo entity/module of the iopll reconfig ip (in this case, I add the parameter in the verilog file altera_iopll_reconfig_core.v of the pll_reconfig_0.ip file).
example:
defparam
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB";
Hope that works for you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
- RichardT_altera
May I know does my latest reply helps ?
Best Regards,
Richard Tan
fst21Hello Richard,
thank you for your answer.
Yes, the change scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB"; works. I had already tried this. However, it is not applicable, because every time the IP is generated, this line has to be added manually.
In the article https://community.intel.com/t5/FPGA-Wiki/Using-set-parameter-for-Quartus-compile-directives-in-VHDL-and/ta-p/735134 a similar problem is described. Only unfortunately it is unclear how this would work with a string.
Many greetings,
Fritjof
- RichardT_altera
I will need to consult the engineering team for alternative way to do it. I am not able to success map it to MLAB using set_parameter as well.
fyi set_parameter how-to use:
Best Regards,
Richard Tan
- RichardT_altera
Just to inform you that I am still pending response from the engineering team.
Regards,
Richard Tan
- RichardT_altera
As it turns out, there's no way to change it other than changing the Verilog code.
Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.
Regards,
Richard Tan
- fst21
That is a great pity. Hopefully it will work in a future release!
Regards,
Fritjof
- RichardT_altera
Would like to clarify that there is currently no plan to enhance this IP unless there is a good justification and demand from the customers.
With that, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
