fst21
New Contributor
New ContributorAssignment RTL_PARAMETER
Hello,
I use the PLL Reconfig Intel FPGA IP core for Arria 10, which uses one fifo each for data and command synchronization. These fifos are mapped as block RAM in M20K despite the small size of onl...
As it turns out, there's no way to change it other than changing the Verilog code.
Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.
Regards,
Richard Tan
