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fst21's avatar
fst21
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3 years ago
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Assignment RTL_PARAMETER

Hello, I use the PLL Reconfig Intel FPGA IP core for Arria 10, which uses one fifo each for data and command synchronization. These fifos are mapped as block RAM in M20K despite the small size of onl...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    As it turns out, there's no way to change it other than changing the Verilog code.

    Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.


    Regards,

    Richard Tan



RichardT_altera's avatar
RichardT_altera
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3 years ago

May I know does my latest reply helps ?


Best Regards,

Richard Tan


fst21's avatar
fst21
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3 years ago

Hello Richard,

thank you for your answer.

Yes, the change scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB"; works. I had already tried this. However, it is not applicable, because every time the IP is generated, this line has to be added manually.

In the article https://community.intel.com/t5/FPGA-Wiki/Using-set-parameter-for-Quartus-compile-directives-in-VHDL-and/ta-p/735134 a similar problem is described. Only unfortunately it is unclear how this would work with a string.

Many greetings,
Fritjof