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fst21's avatar
fst21
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Assignment RTL_PARAMETER

Hello, I use the PLL Reconfig Intel FPGA IP core for Arria 10, which uses one fifo each for data and command synchronization. These fifos are mapped as block RAM in M20K despite the small size of onl...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    As it turns out, there's no way to change it other than changing the Verilog code.

    Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.


    Regards,

    Richard Tan



RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Would like to clarify that there is currently no plan to enhance this IP unless there is a good justification and demand from the customers.


With that, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.