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fst21's avatar
fst21
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3 years ago
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Assignment RTL_PARAMETER

Hello, I use the PLL Reconfig Intel FPGA IP core for Arria 10, which uses one fifo each for data and command synchronization. These fifos are mapped as block RAM in M20K despite the small size of onl...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    As it turns out, there's no way to change it other than changing the Verilog code.

    Most of the reconfig IP in Arria 10 is hardcoded Verilog that Quartus doesn't modify, so you have to directly edit the Verilog as what I did in the previous reply.


    Regards,

    Richard Tan



RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

RTL_parameter is mostly used for PR design flow. I don't think it is applicable in this case.

Reference:

https://www.intel.com/content/www/us/en/docs/programmable/683296/21-4/designpartitionassignmentsrtlparameter.html

https://www.intel.com/content/www/us/en/docs/programmable/683834/22-2/method-2-set-qsf-assignment-for-a-parameterized.html


For generated IP, one way that I can think of is to add the RAM_BLOCK_TYPE defparam in the fifo entity/module of the iopll reconfig ip (in this case, I add the parameter in the verilog file altera_iopll_reconfig_core.v of the pll_reconfig_0.ip file).

example:

defparam

scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB";


Hope that works for you.


Best Regards,

Richard Tan


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