Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

AS configuration error

Hi all,

Stratix II (2s130f780) and EPCS64 (SOIC-16) are used in my project, I have 2 boards, one is ok that is the program can be downloaded with JIC file and init_done pin is high after repower. But the other isn't work.

The second board, I program EPCS64 with JIC file sucessfully about 5 month ago, But now ,when I try to program it with jic file, the error "Can't recognize silicon ID for device " is shown in the Quartus II v8.0. The JTAG mode works well. I can download the pof file sucessfully with AS mode , but init_done pin is low after repower. It looks like the AS interface have some mistakes.

Following steps have been checked:

1. Power supply: FPGA VCCIO = 3.3V, EPCS64 VCC = 3.3V.

2. MSEL pins: MSEL pins are tied to VCCIO or GND correctly. MSEL[3..0] = 1101.

3. Program scheme: I follow the scheme JTAG and AS mode of configuration handbook. The pull-up & pull-down resistors are connected correctly.

4. nStatus is low with 10Kohm pull up 3.3V, but is 3.1V with 5ohm pull up, 2.7V with 10ohm pull up.

5. When power up, I can't observe any low signal on NCSO pin with oscilloscope, and Dclk is low all the time.

I don't know what's the matter with the device?! If somebody knows the solution, help me, please. Thanks in advance.

Regards

njw

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You better shouldn't short nStatus with 5 or 10 ohm "pull-ups", you bring-up device damage.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thank FvM. I just test it. The voltage is different when I change pull up resistance, what is the reason? All power is ok, FPGA don't read data from epcs64, what happens? Can you tell me what shall I do?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Apparently, the board is defective somehow. It either doesn't power up correctly (there are more voltages to check than just VCCIO), nCONFIG isn't released, or the FPGA is damaged. (There may be other reasons, depending on the hardware details).

    Shorting control voltages arbitrarily is like treating the device with a hammer...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for your reply.

    I think that FPGA isn't damaged because I can program it sucessfully with JTAG.

    I guess that it doesn't exit reset after power up, How can I measure the reset states(VCCA and VCCINT)?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I think that has no influence. But in order to be sure you should read the EPCS user manual.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    My comments have been under the assumption, that you correctly reported nStatus has been low all the time from power-on. If you see nStatus low later on, it may simply indicate a failed configuration (without automatic restart enabled). To be sure, you didn't miss a preceeding configuration attempt, you may want to pull nConfig low and check for any reaction at nStatus when releasing it again.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I checked the Quartus settings, and found that option "auto-restart configuration after error" is enabled. Then I pulled low the nConfig pin, but the nStatus pin still low. Now I that the nStatus line from FPGA to EPCS64 is cut, how can i prove it?