Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

arriaII GX Transceiver (SDI)

I'm planning to use EP2AGX65.EP2AGX65 has 8 Transceiver channel(use for SDI).

Channel names(pin name) are from GXB_x0x to GXB_x7x(X=p,n).Banks are QL0 and QL1

Refclk names(pin name) are REFCLK0x,REFCLK1x,REFCLK4x and REFCLK5x.

I think 2 Transceiver bloks(GXB) is here.

First block include GXB_x0x to GXB_x3x.

Second block include GXB_x4x to GXB_x7x.

But I don't understand allocation of REFCLK well.

First block include REFCLK0,1.

Second block include REFCLK4,5.

Is it right?

I want to use SDI refclk 148.5MHz and 148.35MHz.

And I assign 148.35MHz to refclk0.

I assign 148.5MHz to refclk1.

Can the respective transceivers(8 channels) use refclk0 or refclk1?

Can 1 transceiver choose refclk0 or refclk1?

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    "Can the respective transceivers(8 channels) use refclk0 or refclk1?

    Can 1 transceiver choose refclk0 or refclk1? "

    Hi,

    There should be no issue for the transceiver channel to select between two refclk. You can do it through dynamic reconfiguration and switch the refclk source.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    By the way, it is always recommended to check your placement of transceiver and refclk by running Quartus II Fitter compilation. It will help to check against placement rules.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    By the way, it is always recommended to check your placement of transceiver and refclk by running Quartus II Fitter compilation. It will help to check against placement rules.

    --- Quote End ---

    Thank you,bfkstimchan-san

    I have queation of bank location.

    I attach the question.

    There are transceivers on the left side in bank diagram.

    But there are transceivers on the right side in package top view.

    I believe package top view is right.

    There is a comment as “reverse view for package” in bank diagram.

    Why aren't transceivers written on the right in bank diagram?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    I do not have a very clear answer for you. But I believe this might relate to the flip chip thing which make the left and right side toggle.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Agree with bfkstimchan. Generally if we compare the XCVR pin location in pin planner vs chip planner, we will see that the left and right sides will swap.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Agree with bfkstimchan. Generally if we compare the XCVR pin location in pin planner vs chip planner, we will see that the left and right sides will swap.

    --- Quote End ---

    Thank you

    bfkstimchan-san,nic_@-san

    I confirmed that there are Transceivers to the left by a pin-planner.

    By the way, attachment is a sample source of SDI(It was downloaded from a site of Altera).

    Description of following is PLL location in qsf file.

    In the sample,device is EP2AGX125EF35C5ES.

    But when I changed it to EP2AGX65DF29C4 this time, an error occurred.

    When changing a device, how should this part be written?

    set_location_assignment HSSIPLL_X0_Y56_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_tx:u0_A2gxSDI3G_tx|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_tx:gen_tx_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_u3q4:auto_generated|tx_pll0"

    set_location_assignment HSSIPLL_X0_Y59_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_ch4:u1_A2gxSDI3G|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_duplex:gen_duplex_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_f1g9:auto_generated|tx_pll0"
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Agree with bfkstimchan. Generally if we compare the XCVR pin location in pin planner vs chip planner, we will see that the left and right sides will swap.

    --- Quote End ---

    Thank you

    bfkstimchan-san,nic_@-san

    I confirmed that there are Transceivers to the left by a pin-planner.

    By the way, attachment is a sample source of SDI(It was downloaded from a site of Altera).

    Description of following is PLL location in qsf file.

    In the sample,device is EP2AGX125EF35C5ES.

    But when I changed it to EP2AGX65DF29C4 this time, an error occurred.

    When changing a device, how should this part be written?

    set_location_assignment HSSIPLL_X0_Y56_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_tx:u0_A2gxSDI3G_tx|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_tx:gen_tx_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_u3q4:auto_generated|tx_pll0"

    set_location_assignment HSSIPLL_X0_Y59_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_ch4:u1_A2gxSDI3G|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_duplex:gen_duplex_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_f1g9:auto_generated|tx_pll0"
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Thank you

    bfkstimchan-san,nic_@-san

    I confirmed that there are Transceivers to the left by a pin-planner.

    By the way, attachment is a sample source of SDI(It was downloaded from a site of Altera).

    Description of following is PLL location in qsf file.

    In the sample,device is EP2AGX125EF35C5ES.

    But when I changed it to EP2AGX65DF29C4 this time, an error occurred.

    When changing a device, how should this part be written?

    set_location_assignment HSSIPLL_X0_Y56_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_tx:u0_A2gxSDI3G_tx|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_tx:gen_tx_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_u3q4:auto_generated|tx_pll0"

    set_location_assignment HSSIPLL_X0_Y59_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_ch4:u1_A2gxSDI3G|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_duplex:gen_duplex_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_f1g9:auto_generated|tx_pll0"

    --- Quote End ---

    I couldn't attach it. I attach again.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    Sorry as I am not very clear with your inquiries. Are you inquiring how should the following QSF be changed after you change your device? If yes, the TX PLL location is likely to change after you change the device. So, you will need to find out the new TX PLL location to assign to your design.

    "set_location_assignment HSSIPLL_X0_Y56_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_tx:u0_A2gxSDI3G_tx |sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_p ort:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_tx:gen_tx_alt4gxb.u_gxb|alt4 gxb:alt4gxb_component|alt4gxb_u3q4:auto_generated| tx_pll0"

    set_location_assignment HSSIPLL_X0_Y59_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_ch4:u1_A2gxSDI3G|s di_megacore_top:sdi_megacore_top_inst|sdi_txrx_por t:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_duplex:gen_duplex_alt4gxb.u_ gxb|alt4gxb:alt4gxb_component|alt4gxb_f1g9:auto_ge nerated|tx_pll0" "
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Just to add that you check the TX PLL location in chip planner or use the Quartus II Assignment Editor's location drop down selection to assist you.