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Altera_Forum
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10 years ago

arriaII GX Transceiver (SDI)

I'm planning to use EP2AGX65.EP2AGX65 has 8 Transceiver channel(use for SDI). Channel names(pin name) are from GXB_x0x to GXB_x7x(X=p,n).Banks are QL0 and QL1 Refclk names(pin name) are REFCLK0...
Altera_Forum's avatar
Altera_Forum
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10 years ago

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Thank you

bfkstimchan-san,nic_@-san

I confirmed that there are Transceivers to the left by a pin-planner.

By the way, attachment is a sample source of SDI(It was downloaded from a site of Altera).

Description of following is PLL location in qsf file.

In the sample,device is EP2AGX125EF35C5ES.

But when I changed it to EP2AGX65DF29C4 this time, an error occurred.

When changing a device, how should this part be written?

set_location_assignment HSSIPLL_X0_Y56_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_tx:u0_A2gxSDI3G_tx|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_tx:gen_tx_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_u3q4:auto_generated|tx_pll0"

set_location_assignment HSSIPLL_X0_Y59_N135 -to "hsmc_sdi:u0_hsmc_sdi|A2gxSDI3G_ch4:u1_A2gxSDI3G|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_duplex:gen_duplex_alt4gxb.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_f1g9:auto_generated|tx_pll0"

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I couldn't attach it. I attach again.