Arria v SoC FPGA frequency

It depends on the speedgrade of the device. The HPS specific numbers can be found under "Switching Characteristics" -> "HPS Specifications" in the Arria V device datasheet: http://www.altera.com/literature/hb/arria-v/av_51002.pdf At one time the published frequency was lower but Altera was able to bump those specs after the devices came back and binned accordingly.

As for the FPGA portion of the SoC device the fabric switching speed should be identical between SoC and non-SoC devices. Think of the SoC devices as a regular FPGA that just happens to have a large hard silicon block in them.

As for the maximum frequency of the interfaces between the FPGA fabric and HPS block, really the only ones that are significant to care about are the bridges and the FPGA-to-SDRAM interfaces. Those are memory mapped so it's expected that there will be a Qsys system hanging off those interfaces so depending on that design and the IP you use the Fmax will vary. I haven't targetted Arria V SoC yet but I'm sure clearing 200MHz in a real world design should be possible on the faster speed grade parts.

Thanks for the link and the quick response, BadOmen. The document gives net names of the clocks but does not state if these are FPGA clocks. So the MPU and main base clocks are for the ARM cores and the L3 and L4 system respectively. Are the h2f_user* clocks inputs to the FPGA? My confusion arises from the fact that the current device we use is from a different manufacturer and while the FPGA fabric itself (so if the FPGA was purchased as a device on a board, NOT with ARM cores fabb'ed alongside it), the frequency can go to something like 5-600 MHz. With the SoC, it is locked to 250MHz.

We are able to reach this easily with no timing violations. Since we are only limited by FPGA frequency, going to a (significantly) faster FPGA clock would help a lot. However, if the clock bump is only ~50 MHz (so currently we do 250M, new board can do 300M) then it is not worth it because setting up an entirely new piece of hardware and getting started with differnet tools would not be worth the effort.

Hence my question regarding the clock speed in the FPGA fabric itself. Our clock requirements for the other components (ARM, DDR, etc.) are virtually non-existent provided they aren't ridiculously low (300 MHz ARM for example). So then basically, as long as we meet timing and have the highest speed grade, the FPGA can reach the same speed as if the FPGA was purchased alone without the ARM cores?

Thanks again for your response.

Are you using the Arria V SoC Development Kit, do you could be help me i have an issue trying to set-up the Arria, appeared the LED in Red of MAX_ERROR. When you started to work with the Arria doesn't happened this issue to you.

I'm trying to restore the MAX V CPLD with the programmer and reading the user guide help but i don't get the configuration complete, which consists in obtain Config Done LED (D38) illuminates, signaling that the Arria V device configured

successfully.

I appreciate your help,

Alex.