Arria v SoC FPGA frequency

Thanks for the link and the quick response, BadOmen. The document gives net names of the clocks but does not state if these are FPGA clocks. So the MPU and main base clocks are for the ARM cores and the L3 and L4 system respectively. Are the h2f_user* clocks inputs to the FPGA? My confusion arises from the fact that the current device we use is from a different manufacturer and while the FPGA fabric itself (so if the FPGA was purchased as a device on a board, NOT with ARM cores fabb'ed alongside it), the frequency can go to something like 5-600 MHz. With the SoC, it is locked to 250MHz.

We are able to reach this easily with no timing violations. Since we are only limited by FPGA frequency, going to a (significantly) faster FPGA clock would help a lot. However, if the clock bump is only ~50 MHz (so currently we do 250M, new board can do 300M) then it is not worth it because setting up an entirely new piece of hardware and getting started with differnet tools would not be worth the effort.

Hence my question regarding the clock speed in the FPGA fabric itself. Our clock requirements for the other components (ARM, DDR, etc.) are virtually non-existent provided they aren't ridiculously low (300 MHz ARM for example). So then basically, as long as we meet timing and have the highest speed grade, the FPGA can reach the same speed as if the FPGA was purchased alone without the ARM cores?

Thanks again for your response.