Arria v SoC FPGA frequency

It depends on the speedgrade of the device. The HPS specific numbers can be found under "Switching Characteristics" -> "HPS Specifications" in the Arria V device datasheet: http://www.altera.com/literature/hb/arria-v/av_51002.pdf At one time the published frequency was lower but Altera was able to bump those specs after the devices came back and binned accordingly.

As for the FPGA portion of the SoC device the fabric switching speed should be identical between SoC and non-SoC devices. Think of the SoC devices as a regular FPGA that just happens to have a large hard silicon block in them.

As for the maximum frequency of the interfaces between the FPGA fabric and HPS block, really the only ones that are significant to care about are the bridges and the FPGA-to-SDRAM interfaces. Those are memory mapped so it's expected that there will be a Qsys system hanging off those interfaces so depending on that design and the IP you use the Fmax will vary. I haven't targetted Arria V SoC yet but I'm sure clearing 200MHz in a real world design should be possible on the faster speed grade parts.