Arria V Gz ibis model - DDR3

Hi everyone,

I'm trying to set up a Hyperlynx simulation for a design with 2 DDR-3 ICs and a Arria V Gz that interfaces with the 2 DDR3 ICs. I want to simulate 4 classes of signals.

1 - Clock

2 - Address (driven from the FPGA to the 2 DDr3 ICs)

3 - Write Data (driven from the FPGA to 1 DDR3 IC)

4 - Read Data (driven from a DDR3 IC to the FPGA).

Alas, I'm not able to simulate case 4 since there does not seem to be any support in the ibis model, the only models I have for DDR_DQ pins (on the FPGA side) is

sstl15i_ctio_d12s1 12mA, Off, Slew Rate: FAST

sstl15i_ctio_d4s1 4mA, Off, Slew Rate: FAST

sstl15i_ctio_s1 Minimum Current, Off, Slew Rate: FAST

sstl15i_ctio_d6s1 6mA, Off, Slew Rate: FAST

sstl15i_ctio_d8s1 8mA, Off, Slew Rate: FAST

sstl15i_ctio_d10s1 10mA, Off, Slew Rate: FAST

sstl15i_ctio_r50 Default, Series 50 Ohm without Calibration, Slew Rate: FAST

sstl15i_ctio_r50c Default, Series 50 Ohm with Calibration, Slew Rate: FAST

It seems that all these models are for writing data to the DDR3 and not reading data from the DDR3. has anyone had any luck making the Hyperlynx simulations work with an Arria V Gz? I was also thinking of maybe simulating it with a generic Stratix5 model instead to see if it helps.