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Altera_Forum
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12 years ago

Arria V Gz ibis model - DDR3

Hi everyone, I'm trying to set up a Hyperlynx simulation for a design with 2 DDR-3 ICs and a Arria V Gz that interfaces with the 2 DDR3 ICs. I want to simulate 4 classes of signals. 1 - C...
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Altera_Forum
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11 years ago

hie Benjamin_Couillard,

have you resolved this issue? if no...

can i ask what you mean when you say that "the models are for writing data to the DDR3 and not reading data from DDR3"?

is it becos the only available models for sstl15 are input/output models? are you looking specifically for input_only IBIS models, or you are looking for a specific I/O standard that is supported in AV but just not available in the AV IBIS model?

thanx