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KSMark's avatar
KSMark
Icon for New Contributor rankNew Contributor
3 years ago

Arria V Avalon-MM Hard IP for PCIe PLL lock

Is there a pin from the Avalon-MM Arria V Hard IP for PCI Experess that I can monitor the serdes_pll_locked signal or someother downstream signal I can infer the pll lock state. I am getting an occasional reset from the PCIe core(during and ESD event). I have mostly ruled out the reset going into the part and would like to determine if my clock is remaining stable.

I am using quartus version 18.1.0 and the part is an 5AGXMB7G4F35I5.

3 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,

    You can create another pin connected to the serder_pll_locked or coreclkout_hip clock signal with platform designer to monitor the pll locked signal.

    regards,
    Farabi

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    attached is userguide

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,


    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    regards,

    Farabi