Forum Discussion

KSMark's avatar
KSMark
Icon for New Contributor rankNew Contributor
3 years ago

Arria V Avalon-MM Hard IP for PCIe PLL lock

Is there a pin from the Avalon-MM Arria V Hard IP for PCI Experess that I can monitor the serdes_pll_locked signal or someother downstream signal I can infer the pll lock state. I am getting an occa...
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,

You can create another pin connected to the serder_pll_locked or coreclkout_hip clock signal with platform designer to monitor the pll locked signal.

regards,
Farabi