KSMarkNew Contributor4 years agoArria V Avalon-MM Hard IP for PCIe PLL lock Is there a pin from the Avalon-MM Arria V Hard IP for PCI Experess that I can monitor the serdes_pll_locked signal or someother downstream signal I can infer the pll lock state. I am getting an occa...Show More
Farabi_AlteraRegular Contributor4 years agoattached is userguideArria V Hard IP for PCI Express User Guide - Altera.pdf13.1 MB
Recent DiscussionsError (209014): CONF_DONE pin failed to go high in device 1.Implementation of lower data rate.eFUSE : Agilex F series and AGilex I series PCIe cardIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAEP4CGX22CF19C8N Failure Short D8 to C8