Forum Discussion
Honored ContributorArria V 1.5v PCML Read
Hi,
I would like to use signal tap to read the value on a number of 1.5v PCML pins, however, using signal tap to probe these pins causes an error stating that the pins must have a fanout of 1. I looked on the forum for a solution (http://www.alteraforum.com/forum/showthread.php?t=20991&highlight=pcml+signal+tap) and it seems like there is a GXB ip core available that will fix this issue, however the FPGA that I am using (5AGTFD7K3F40I3) does not have this core. Any suggestions on how to tackle this problem and read from the PCML pins?6 Replies
Altera_ForumThe Arria V GT device that you are using should support the transceiver IP ie Native PHY, Custom PHY to allow the usage of the transceiver pins.
- Altera_Forum
"1) What does FPGA fabric transciever interface width mean? Doesn't the transciever just interface with a pair of differential pins on the FPGA?
" The fabric - XCVR interface width is referring to the data width between the PCS of XCVR and the core fabric. A transceiver's transmitter primary usage is to convert parallel data into serial data and transmit out on a differential pair. For the receiver, the process is the other way round. Outside the FPGA, you are seeing a pair of pins but inside there are more data lines. - Altera_Forum
Thank you for the reply, I think it's helped guide me into the right direction. I found two articles related to transceivers in Arria V devices:
Transceiver Basics for Arria V Devices (http://bimansirphysics.webs.com/documents/av_54002transreceiver%20basic%20aletra.pdf) Arria V Device Handbook - Volume 2: Transceivers (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/arria-v/av_5v3.pdf) However, I can't find a clear explanation on what protocol the PMA uses to deserialize data coming from the PCML pins. How does the deserializer in the PMA decide how to convert serial data into parallel data? - Altera_Forum
Hi,
The PMA does not have a specific protocol to serialize or deserialize data. Basically what it does it convert the parallel data to/from serial data based on your configuration ie data width, data rate. - Altera_Forum
"2) How is the parallel data collected? What parallel data are they referring to? Isn't the data being sent serially to the FPGA (via the PCML pin)?
" The parallel data will be collected in internal FIFOs and then pass to the FPGA core. The serial data is of much faster frequency which could not handled by the core. - Altera_Forum
"3) What are dedicated transciever pins and why does the output of a transciever pin (that has no signal on the line) connected to the custom PHY produce non-zero output values?
" Transceiver pins on the FPGA can only be used for high speed transceiver application. You cannot use it for other IO purpose. The non-zero output values might be due to noise or if you have 8b10b block enabled, it might decode 0 data to non-zero values.
