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Altera_Forum
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10 years ago

Arria V 1.5v PCML Read

Hi, I would like to use signal tap to read the value on a number of 1.5v PCML pins, however, using signal tap to probe these pins causes an error stating that the pins must have a fanout of 1. ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

"2) How is the parallel data collected? What parallel data are they referring to? Isn't the data being sent serially to the FPGA (via the PCML pin)?

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The parallel data will be collected in internal FIFOs and then pass to the FPGA core. The serial data is of much faster frequency which could not handled by the core.