Arria II - GX Jitter performance

I'm not convinced GX parts will run at 6.375Gbps.

The maximum refclk for the GX parts is 622.08MHz. The serializer then gives a maximum serial data rate of 6.22Gbps. The GZ parts support a 637.5MHz refclk (and higher) giving the 6.375Gbps you're after.

So, I think the devil is in the detail and, perhaps, explains why there are no references to anything over 6Gbps in the datasheet for GX parts.

Cheers,

Alex

Hi Alex,

Thank you for the reply. Yes I do find it strange that the company has gone for such an FPGA with a very little information on jitter at such a high data rate. But we have tested the data rate and we are able to achieve about 6.25 Gbps. Unfortunately we are not able to analyse why we are getting such a high jitter. Moreover to measure jitter at such a high data rate we need an expensive oscilloscope.

So that is one of the reason why I asked as to why there is not much information on the jitter specification. However I was able to read about Transmitter specifications for GX and Transmitter REFCLK phase jitter (rms) for 100 MHz REFCLK is 3ps.

REFCLK phase jitter (rms) for 25MHz is 6ps i.e based on the formula provided in the NOTE section by Altera.

Since my refclk is 25Mhz, can this be one of the reason and using a higher freq ref clk can solve my jitter issues??

regards,

Sreeni

Perhaps I should have said - 'I'm not convinced GX parts should be run at 6.375Gbps'. However, I still cannot find anything specifically stating that, only the implied info I've already given. I'd be concerned whether Altera 'support' this if it's out of spec (assuming it is out of spec). There are plenty of examples of devices operating beyond their spec, but will all devices, across temperature, work reliably.

The Transmitter REFCLK phase jitter will be the maximum the PLL can tolerate before it looses lock, or at best operate properly - the PLLs jitter tolerance. It's not an indication of the jitter transfer.

Instinctively, I would suggest running with a higher frequency ref clock should help. However, I can't find anything to support this in the Arria II docs.

You might consider cascading PLLs. Altera suggests "By cascading PLLs, you can use this path to reduce clock jitter." Although it doesn't mention your particular device in the text it does mention using PLL's 1 & 4, which your device does have. Look at the "Cascading PLLs" section, page 5-22, in clock networks and plls in arria ii devices (http://www.altera.com/literature/hb/arria-ii-gx/aiigx_51005.pdf).

Cheers,

Alex

The Arria II GX -I3 parts do support operation at 6.375Gbps. We've tested our parts at that speed using the Altera transceiver toolkit.

Our design has two SATA III 6Gbps interfaces, one internal (to an on-board SSD) and one external (eSATA port). The internal port runs reliably at 6Gbps, but the eSATA port does not. To isolate the problem we used the transceiver toolkit with the eSATA port on our board connected to a transceiver on the Arria II GX dev kit (-I3 version) through an HSMC daughter card. With the transceiver toolkit we were able to run our eSATA port reliably at 6.375Gbps talking to the dev kit. With this setup the FPGA on our board only contained the transceiver toolkit logic. But when we try to interface with an external SSD through the eSATA port at 6Gbps with our full design (this is a GX125 part that is about 85% full), it just will not run reliably.

We feel that we validated the eSATA channel with the transceiver toolkit. So our theory is that increased jitter with our full design running is likely one of the factors that prevents the eSATA port from running reliably. We don't have the tools required to prove this, but it makes sense.

My point here is that even if Altera spec'd the jitter for the transceiver there would be assumptions built into that number. And depending on your design those assumptions may not be valid. I think the only way to really know how the thing will behave is to build a board and test it under the conditions in which it will be operating.