Arria II - GX Jitter performance

Perhaps I should have said - 'I'm not convinced GX parts should be run at 6.375Gbps'. However, I still cannot find anything specifically stating that, only the implied info I've already given. I'd be concerned whether Altera 'support' this if it's out of spec (assuming it is out of spec). There are plenty of examples of devices operating beyond their spec, but will all devices, across temperature, work reliably.

The Transmitter REFCLK phase jitter will be the maximum the PLL can tolerate before it looses lock, or at best operate properly - the PLLs jitter tolerance. It's not an indication of the jitter transfer.

Instinctively, I would suggest running with a higher frequency ref clock should help. However, I can't find anything to support this in the Arria II docs.

You might consider cascading PLLs. Altera suggests "By cascading PLLs, you can use this path to reduce clock jitter." Although it doesn't mention your particular device in the text it does mention using PLL's 1 & 4, which your device does have. Look at the "Cascading PLLs" section, page 5-22, in clock networks and plls in arria ii devices (http://www.altera.com/literature/hb/arria-ii-gx/aiigx_51005.pdf).

Cheers,

Alex