Honored Contributor
Honored ContributorThe Arria II GX -I3 parts do support operation at 6.375Gbps. We've tested our parts at that speed using the Altera transceiver toolkit.
Our design has two SATA III 6Gbps interfaces, one internal (to an on-board SSD) and one external (eSATA port). The internal port runs reliably at 6Gbps, but the eSATA port does not. To isolate the problem we used the transceiver toolkit with the eSATA port on our board connected to a transceiver on the Arria II GX dev kit (-I3 version) through an HSMC daughter card. With the transceiver toolkit we were able to run our eSATA port reliably at 6.375Gbps talking to the dev kit. With this setup the FPGA on our board only contained the transceiver toolkit logic. But when we try to interface with an external SSD through the eSATA port at 6Gbps with our full design (this is a GX125 part that is about 85% full), it just will not run reliably. We feel that we validated the eSATA channel with the transceiver toolkit. So our theory is that increased jitter with our full design running is likely one of the factors that prevents the eSATA port from running reliably. We don't have the tools required to prove this, but it makes sense. My point here is that even if Altera spec'd the jitter for the transceiver there would be assumptions built into that number. And depending on your design those assumptions may not be valid. I think the only way to really know how the thing will behave is to build a board and test it under the conditions in which it will be operating.
