Forum Discussion
Hello Fabian,
I checked with internal team, the size of the bitstreams varies, and it does not have a fixed size.
Notes: The configuration bitstream is always the last block interpreted by FPGA, regardless of total image size.
So the it is important to understand that the last 576 bytes is relative to the end of the image, not an absolute flash address.
This block is processed before the FPGA can even attempt a configuration.
It consists of :
1- Configuration end markers - signal end of bitstream
2- CRC/Checksum data - to verify data integrity
3- Device configuration info - to confirm compatibility
4- RSU-related metadata - Required before fallback
If corrupted:
1- FPGA doesn't know this image is failed
2- FPGA only know this image is invalid
3- Impact to - No fallback path is taken
I am checking how to validate the bitstream before we can proceed with RSU. I will get back after getting the confirmed answer.
regards,
Farabi