Occasional ContributorArria 10 HPS, SPIM mapped to FPGA
I am trying to wire up a SPIM peripheral from the Arria 10 HPS to FPGA IO pins, and there is one point of confusion in the technical reference manual.
In Table 214, the naming of pins, there is an output enable for the MOSI line when using the peripheral as a master. The name of this signal is given as "spim_mosi_oe"
This matches the RTL signal names.
However in Figure 112, a different naming convention is used:
Could you confirm whether the output enable is active high as implied by the signal naming:
assign mosi = spim_mosi_oe ? spim_mosi_o : 1'bz;
Or active low (as in the diagram):
assign mosi = spim_mosi_oe ? 1'bz : spim_mosi_o;
So my issue was actually a pin assignment rather than the output enable logic.
After a bit of testing, it would seem for the Arria 10 the diagram in the technical reference manual is wrong. The output enable is active high
Following the signal naming convention not the diagram. The output enable is active high:
assign mosi = spim_mosi_oe ? spim_mosi_o : 1'bz;
