Forum Discussion

jdun's avatar
jdun
Icon for New Contributor rankNew Contributor
5 years ago

ARRIA 10 driving unpowered I/O pins

In the A10 handbook Chapter Power Management in Intel Arria 10 Devices it has Table 128.

I have a few questions about this table. Isn't all I/O Tristated and have an optional 25Kohm pull-up during power-up? So why does this table matter?

Is this talking about interally driving pins with FPGA code, or externally driving pins?

For the 3VIO banks under Drive to GND, under Power-Up, is has a -, or " Not Applicable". Does that mean I can't tie some 3VIO I/O directly to PCB ground? Or does that mean I can't drive an unpowered I/O bank pin with FPGA code? On the Board I am designing it has ModAbs pin. It is pulled high, unless there is a module connected. When a module is connected is it tied directly to ground. Does this mean I need a tri-state buffer.

I have the same question about Driving to VCCIO. If it is the Same Power Supply and powering the same VCCIO as the FPGA, and powers up at the same time is it ok to be directly tied to a IO pin.

3VIO pins are 3.3v tolerant. If there is an external I2C that is powered on before the FPGA. Is it ok to pull I/O high to 3.3 V through a 1-10K ohm resistor, before power-up? For a LVDS bank it would be ok to have a pull-up, because it would be under 10mA, but there is no limit listed for 3VIO bank, and LVDS banks aren't 3.3 V tolerant.

Does this basically mean all 3VIO pins that are tied to PCB ground, tied to VCCIO, or even pulled-up need a external tri-state buffer on the PCB?

Thanks

10 Replies

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Jonathan,


    Is this talking about interally driving pins with FPGA code, or

    externally driving pins?

    --> It is related to driving pins externally.


    The table is related to some of the options available for "Hot-socketing" i.e. driving pins externally during power-up.


    Please refer the Arria 10 Pin connection guidelines for how to manage unused pins on board.

    https://www.intel.com/content/www/us/en/programmable/documentation/wtw1404286459773.html


    Regards.


    • jdun's avatar
      jdun
      Icon for New Contributor rankNew Contributor
      5 years ago

      Thank You, So it appears you can connect unused pins to ground, even during power-up. So I should be able to tie used pins to ground during power up. I don't plan on "Hot Socketing", there is no plan to connect the board while the power is on. Some devices on the PCB will power up before the FPGA. I was just wondering why it appeared to me that you couldn't have pins tied to ground, before power-up. but it looks like that only applies to hot socketing.

      What about having pins connected to VCCIO? Is it ok to have external devices powered by the same VCCIO? I am thinking as long as it is the same VCCIO that power that FPGA VCCIO bank and they power up at the same time, it should be ok. The problem happens when an unpowered FPGA gets a external voltage on it's pins

      I am also assuming that 10K pull-ups to 3.3V should be ok also, since that would be very little current.

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi Jonathan,

    Sorry for the late response. Had discussion with experts on this and here is the finding:

    The purpose of this table is explain the used I/O pin power up and power down condition. Example, the IO pin at 3VIO, if used as input pin, basically we don’t encourage user to drive signal into the I/O pin during power up or power down condition.

    It means you cannot connect the 3VIO pins directly to GND or VCCIO on board.


    Power-up and power-down sequence should be followed and the unused pins should be treated as mentioned in the Pin connection guidelines.


    Regards.


    • jdun's avatar
      jdun
      Icon for New Contributor rankNew Contributor
      5 years ago

      That still confuses me. I guess I should just put tri-state buffers on the 3VIO pins in question. I was trying to avoid extra parts, and that's what I used the 3VIO banks.

      Power down doesn't concern me as much as power-up. On power-up nothing is configured yet. The FPGA doesn't know which pins are inputs or outputs. The table shows 3VIO can be tied to ground on power down, but not on power up.

      The pins in question come from an SFP module. It has a MODSABS pin. If there is a SFP module present it is tied directly to ground. There are also other pins that could be directly tied to ground on Power up. I guess I just have to externally tri-state them.

      Could I fix this if I used the DEV_OE pin?

      • jdun's avatar
        jdun
        Icon for New Contributor rankNew Contributor
        5 years ago

        This brings me to another question. For power-up is this talking about unpowered pins, or not yet configured pins? From my understanding input, output, or unused pins are configuration dependent. So right after power up all pins are tri-stated inputs, with 25K pull-ups, right? Pins only become an input, or output, or unused after configuration, which is after power-up. So at power-up it shouldn't matter if a pin is later configured as a input and output, or unused. Configuration doesn't have to happen at power-up and can happen a while after powerup. So does this mean no 3VIO pins can be tied to ground or any voltage. It has to be tristated or floating externally?

        Can you drive pins after power-up and before configuration?

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI Jonathan,


    If you want a constant value for a certain input pin driven from the board, then instead of just a resistor tie to VCC or GND, it recommended to use a transistor or mux logic to control the pin. The pin should not be driven at power up from the board. The external driving logic should be enabled after complete power-up and configuration only.


    Regards.


    • jdun's avatar
      jdun
      Icon for New Contributor rankNew Contributor
      5 years ago

      Will DEV_OE work to tristate all pins, or does it need to be external? Also If I am understanding you right this applies to unused pin. So all 3VIO pins, need to be left floating at powerup? Even the CLK and PLL pins?

      This basically means I have to put external try states on all the 3VIO pins I use. Thumb switches need an external tristate, because they are either pulled high or low. Even LEDs need an external driver, even though you can set 3V LVTTL to 24mA. Because at power up the LEDs could possibly pull the pins high or low with a good amount of current.

      I2C pins( or any open drain) also need a bidirectional tristate, because they cannot be pulled high, and especially if they is a chance they could be low on power up.

      Is this a little quirk with ARRIA 10s I don't remember seeing this on previous FPGAs. And it's weird it really only applies with the 3VIO. the LVDS banks can handle 10mA per pin at power up and no more than 100mA per bank, and can be tied to gnd.

      I guess I will just use tristates or move the pins to another bank and use Level Translators.

    • jdun's avatar
      jdun
      Icon for New Contributor rankNew Contributor
      4 years ago

      Thank You, I ended up moving many pins to LVDS banks, which can be tied to GND on power up. They also can be tied to VCCIO through a pull-up as long as you stay under 10mA. And the I/O I didn't move I use this part. It is a bidirectional level shifter with an OE. https://www.ti.com/product/TXS0108E I figure I better follow the specs.