New Contributor
Regular ContributorHi Jonathan,
Sorry for the late response. Had discussion with experts on this and here is the finding:
The purpose of this table is explain the used I/O pin power up and power down condition. Example, the IO pin at 3VIO, if used as input pin, basically we don’t encourage user to drive signal into the I/O pin during power up or power down condition.
It means you cannot connect the 3VIO pins directly to GND or VCCIO on board.
Power-up and power-down sequence should be followed and the unused pins should be treated as mentioned in the Pin connection guidelines.
Regards.
New ContributorThat still confuses me. I guess I should just put tri-state buffers on the 3VIO pins in question. I was trying to avoid extra parts, and that's what I used the 3VIO banks.
Power down doesn't concern me as much as power-up. On power-up nothing is configured yet. The FPGA doesn't know which pins are inputs or outputs. The table shows 3VIO can be tied to ground on power down, but not on power up.
The pins in question come from an SFP module. It has a MODSABS pin. If there is a SFP module present it is tied directly to ground. There are also other pins that could be directly tied to ground on Power up. I guess I just have to externally tri-state them.
Could I fix this if I used the DEV_OE pin?
New ContributorThis brings me to another question. For power-up is this talking about unpowered pins, or not yet configured pins? From my understanding input, output, or unused pins are configuration dependent. So right after power up all pins are tri-stated inputs, with 25K pull-ups, right? Pins only become an input, or output, or unused after configuration, which is after power-up. So at power-up it shouldn't matter if a pin is later configured as a input and output, or unused. Configuration doesn't have to happen at power-up and can happen a while after powerup. So does this mean no 3VIO pins can be tied to ground or any voltage. It has to be tristated or floating externally?
Can you drive pins after power-up and before configuration?
New ContributorOne more question. I was looking into just putting a resistor on the I/O pins to limit possible current, and was trying to find the Current rating on 3VIO pins. I found conflicting results. Attached is what I found. The max current is 2ma LVTTL, or 0.1ma for LVCMOS. But the programable current max is 24mA, and 2mA or 0.1 mA is not even an option. If it in 0.1mA even a 10Kohm pullup to 3.0V would be too much current.
