Arria 10 clock problem

Hi, you will get this error might due to you have constrained an I/O pin or group of pins to a location, bank, or region that could not support the required I/O standard.

You have to make sure that you have not assigned pins requiring a particular I/O standard to banks that do not support the standard, and that you have not constrained too many I/O pins requiring a particular voltage to a region that does not have enough I/O pin locations capable of supporting the selected voltage.

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Hello,

Im implementing a custom design using Arria 10 (10AX115N4F40I3SG).

During Place and Route, the following problem related to clock asiignement appears: :confused:

Error (179009): Could not find enough available I/O pin locations that supports the Current Mode Logic (CML) standard (2 locations affected)

Info (175029): AJ5

Info (175029): pin containing PIN_AJ5

The clock im using is mapped to the input PIN_AJ5 of the FPGA on the board.

I even checked this PIN in the FPGA pins document and it's a clock input.

Does anyone had a similar problem using Arria10? :confused::confused:

note:

- Im using Quartus v14.1.

- This clock is mapped in internal PLL in my design.

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I did a quick check with my Quartus II 15.0 on your device, the pin AJ5 is a normal clock input pin but not transceiver refclk pin. You can try to use other IO standard ie LVDS, LVPECL to see if can pass the compilation.

Hello,

Thank you for your replies.

In fact, as bfkstimchan said the pin AJ5 is a normal clock. I even tried 3 others clock inputs and I still have the same problem.

Anyway, since this clock input feeds an internal PLL in my design (Altera normal PLL IP), i replcaed this PLL with Altera IOPLL IP.

The problem is solved!

I think that the error is related to the placement of the normazl Altera PLL during Plca e and Route phase.

Thnak you all for your help.

Best regards.

Just to add on, each bank have 4 dedicated refclk, but only 1 (any) of the 4 can reach the bank's IOPLL.

Also, you cannot connect bank A refclk to bank B IOPLL.

From what I know Arria10 IOPLL is different from the past devices. They are not arranged as center/corner PLLs.

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Hello,

Thank you for your replies.

In fact, as bfkstimchan said the pin AJ5 is a normal clock. I even tried 3 others clock inputs and I still have the same problem.

Anyway, since this clock input feeds an internal PLL in my design (Altera normal PLL IP), i replcaed this PLL with Altera IOPLL IP.

The problem is solved!

I think that the error is related to the placement of the normazl Altera PLL during Plca e and Route phase.

Thnak you all for your help.

Best regards.

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Glad to hear that you have managed to resolve your issue and thanks for sharing the resolution.