--- Quote Start ---
Hello,
Im implementing a custom design using Arria 10 (10AX115N4F40I3SG).
During Place and Route, the following problem related to clock asiignement appears: :confused:
Error (179009): Could not find enough available I/O pin locations that supports the Current Mode Logic (CML) standard (2 locations affected)
Info (175029): AJ5
Info (175029): pin containing PIN_AJ5
The clock im using is mapped to the input PIN_AJ5 of the FPGA on the board.
I even checked this PIN in the FPGA pins document and it's a clock input.
Does anyone had a similar problem using Arria10? :confused::confused:
note:
- Im using Quartus v14.1.
- This clock is mapped in internal PLL in my design.
--- Quote End ---
I did a quick check with my Quartus II 15.0 on your device, the pin AJ5 is a normal clock input pin but not transceiver refclk pin. You can try to use other IO standard ie LVDS, LVPECL to see if can pass the compilation.
Honored Contributor
