Arria 10 clock problem

Hello,

Thank you for your replies.

In fact, as bfkstimchan said the pin AJ5 is a normal clock. I even tried 3 others clock inputs and I still have the same problem.

Anyway, since this clock input feeds an internal PLL in my design (Altera normal PLL IP), i replcaed this PLL with Altera IOPLL IP.

The problem is solved!

I think that the error is related to the placement of the normazl Altera PLL during Plca e and Route phase.

Thnak you all for your help.

Best regards.