Hi All We have a PCB board we designed with AMD 8860 GPU that sends DP video to Aria V Display Port core (Qsys). In some of our boards we sometimes have DP connection issues. The video signal goes to altera_xcvr_native_av and when RX is out of lock we see multiple retries on the DP AUX channel. We came across this bug: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-does-the-intel--displayport-receiver-ip-with--enable-gpu-con.html in our case the enable GPU is not checked. Can anyone confirm this issue is also applicable to Aria V Display Port? Thanks Ariel

relsaar, Thank you for posting in the Intel® Communities Support.In reference to your inquiry, in order for us to be able to provide the most accurate assistance for this scenario, I will transfer your thread to the proper department, they will further assist you with this matter.Regards,Albert R.Intel Customer Support TechnicianA Contingent Worker at Intel

Hi Ariel,I looked at the KDB link. You can see at the top, it mentioned the affected FPGA family is just Arria 10 and Stratix 10 which means Arria V is not affected by this issue.Anyway, I always recommend user to upgrade to latest Quartus Standard edition version if possible to mitigate the risk of known issue from older Quartus version.Btw, you mentioned Rx loose lock. Are you referring to Rx channel CDR locked to data signal or some other status signal ?Common factor that will caused CDR to loose lock are like below high PPM different on CDR refclk - checked your on board crystal or clock generator quality. Bad signal integrity on CDR refclk - same debug approach as aboveBad signal integrity on data transfer on Rx channel - reduce your video resolution to reduce the DP bandwidth from 5,4G to 2.7G or even 1.67G to help isolate signal integrity issueYou can also use DP example design to dump the MSA log to check if you observe high bit error rate (BER) on the 4 DP channel or 2 DP channelThanks.Regards,dlim

Hi dlim Thank you for your fast and detailed response. I understand the Arria V and 10 Display Port IP core is different and the bug report I mentioned earlier is not relevant for our problem. (please confirm) Regarding your suggestion to migrate to a new version of Quartos - our Display port core was bought from Bitech (which was later bought by Altera) and is not supported above Quartos 16.0. We tried to compile on Quartos 20.1 the reference design of current display port core but could not get an evaluation *.sof file. If migrating will solve the issue we will be happy to purchase a license or maintenance. the lock signal I mentioned earlier is the output of the Arria V Transceiver Native PHY. The setting of this core has a PPM detector threshold that is set to 1000 PPM (similar to reference design) while our reference clock Oscillator is +/- 20PPM (see attached spec). I figure high value on the PPM detector makes the design more robust? Our video resolution BW is already 1.62G and the signal looks good on debug monitor while it is locked, however the reference clock seems a bit noisy when we probe it with a deferential probe (see attached image). do you recommend to add "Input Termination" at "OCT 100 Ohms" in the assignment editor? Our differential ref clock pin is currently set to I/O Standard LVDS. Please see clk ref schematics image attached below, the right side nets "DP REF CLK+" and "DP REF CLK-" are connected directly to the Arria V FPGA. We tried to check the reference design for dumping the MSA log but it is not clear how to apply it (Please send link or more info on this issue) Thanks Ariel

Hi,I think the first thing we need to clarify is which DisplayPort IP that you are using here ? Are you using Bitec DisplayPort IP or Altera DisplayPort IP ?If you are using Bitec DisplayPort IPThen my suggestion to you will be to engage back Bitec for better issue support I also share same concern with you on IP upgrade capability. Since this is not Altera IP, Intel Engineering won't support IP migration to latest Quartus version. Bitec should has their own IP migration strategy. Pls consult Bitec accordingly Else if you are using Altera DisplayPort IPThen it only make sense for you to perform IP migration to latest Quartus version.Byright evaluation license should still able to generate sof file but I am not familiar with licensing issue. Perhaps you can contact your local FAE for licensing support ? I presume you are referring to Rx channel CDR lock monitor signal (rx_is_lockedtodata) Attached is the CDR loose lock debug checklist for your reference. It's targeted for C10 GX FPGA but the debug methodology is more or less the sameIf you confirmed CDR is indeed loose lock on your board then there is no point to dump MSA log to debug DisplayPort anymore because your Rx transceiver channel already failed to sample/receive data in the first place before the data is passed to DisplayPort RX IPWhen PPM threshold setting = 1000, it means it allow max PPM drift until 1000ppm while your oscillator ppm is only +-20ppm which is good. So, maybe ppm is not the issue hereYup, your 135MHz refclk signal probe result looks bad but I am not sure is it due to your board design issue, or your probing contact issue or oscilloscope bandwidth issue ?Did you manually hold your diff probe or use some tool to hold it or solder the probe tip on board ? Also is your oscilloscope bandwidth at least 3x or 5x of 135MHz ?Lastly, yes. Enable 100ohm OCT insides FPGA should help to improve the LVDS signal termination. Pls try it out.You also mentioned your 1.67G Rx data transfer signal quality should be good May I know how do you check it ? Did you run board simulation or use transceiver toolkit to to perform loopback testing on board ?Thanks. Regards,dlim

Aria V Display Port core sometimes disconnected

50 Replies

Deshi_Intel
Regular Contributor
5 years ago
Hi,

FPGA ALM is insides FPGA core logic. Hard periphery IP like transceiver channel count won't matter to it.

So, you want to either
(A) try out bigger AV FPGA with higher ALM count
Looking at the excel file is not safe.
It's better for you to change the example design AV device OPN and test out fitter compilation directly.
or (B) check to see if you can reduce some feature in DisplayPort IP to reduce the ALM usage in your existing AV FPGA
I know reducing bit per colour definitely helps
You can also check to see if "support CTS test automation" setting is enabled in DP IP. Just disable it and regenerate IP again.

Thanks.

Regards,
dlim
Deshi_Intel
Regular Contributor
4 years ago
HI,

Just to follow up what's the latest status update ?

Did you manage to port over the example design to run some testing ?

Thanks.

Regards,
dlim
- relsaar
  New Contributor
  4 years ago
  Hi,
  I managed to compile the example design with minimal changes successfully but unfortunately our pld is too small.
  I ordered a bigger arria V and as soon as ill get it I plan to assemble it and test the BER.
  Thanks
  Ariel
Deshi_Intel
Regular Contributor
4 years ago
Hi,

Thanks for the update.

In this case, may I suggest for case closure first as I can't let the case idle without activity update for too long ?

Once you get your new FPGA and rerun hardware testing, then you can file new forum post to Intel to resume debug support discussion.
Just tag the forum title with something like "continuous support from previous AV DP case 04894952" then the case will be routed to me to continue to help you up.

Thanks for your understanding.

Regards,
dlim
- relsaar
  New Contributor
  4 years ago
  Hi,
  
  OK - please close the case and I'll open a new one as you suggested.
  
  Thnaks for your support.
  
  Ariel Saar
Deshi_Intel
Regular Contributor
4 years ago
HI,

Thanks for your understanding

Alright, I will proceed to close this case first.

Regards,
dlim
relsaar
New Contributor
4 years ago
Hi

Since our 5AGXMA1D4F27I5N is too small to host Intel example design we purchased 5AGXMA3D4F27C5N and assembled it on our board.

According to the migration design guide it supposed to be direct replacment however auto detect failed on reading devise ID.

I'm going to validate power, clk and jtag signals of the new PLD devise however can you please help me verify no schematice change is required after such migrating?

Thanks

Ariel

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Aria V Display Port core sometimes disconnected

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