Aria V Display Port core sometimes disconnected

Hi,

FPGA ALM is insides FPGA core logic. Hard periphery IP like transceiver channel count won't matter to it.

So, you want to either

• (A) try out bigger AV FPGA with higher ALM count
  • Looking at the excel file is not safe.
  • It's better for you to change the example design AV device OPN and test out fitter compilation directly.
• or (B) check to see if you can reduce some feature in DisplayPort IP to reduce the ALM usage in your existing AV FPGA
  • I know reducing bit per colour definitely helps
  • You can also check to see if "support CTS test automation" setting is enabled in DP IP. Just disable it and regenerate IP again.

Thanks.

Regards,

dlim