Honored ContributorI have designed a CPU and synthesis to FPGA, I can see how mant logical element,register only, Combinational with a register, LUT these information in the compilation report. And I have seen what this mean in the cyclone 3 handbook. I just want to ask is there any information about the area of these each part? Or is there any way to see the total area of my design? Thanks!
Honored Contributorvisually? If yes, go to chip planner
Honored ContributorThank you for your reply. I have had a simple view of the chip planner. Can it know the exactly size of my design? Since I invetegate the infunence of reducing instruction sets. I want to know the change of area when I reduced the instruction sets. Thank you!
Honored ContributorNot that I know of! Why won't the "Resource Utilization by entity" not help you?
Honored ContributorThank you for your reply. Can you say it more detail? As sometimes when I reduced the instruction, the compilation report shows that the logic elements which the design used is increased. But in theory, when I reduced the instructions, the power consumption of my CPU should reduced. But I can't see this result from the the number of logic elements it used. Since large area means more power consumption. So I want to know the change of area size of my design to see the change of power consumption of my CPU core. Thank you!
Honored ContributorThere is a tool called as "power play" in quartus.
http://www.altera.com/literature/hb/qts/qts_qii53013.pdf I haven't used this option. I am not sure if this helps you but take a look at it.
