Area of the design

Thank you for your reply. Can you say it more detail? As sometimes when I reduced the instruction, the compilation report shows that the logic elements which the design used is increased. But in theory, when I reduced the instructions, the power consumption of my CPU should reduced. But I can't see this result from the the number of logic elements it used. Since large area means more power consumption. So I want to know the change of area size of my design to see the change of power consumption of my CPU core. Thank you!