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Altera_Forum
Honored Contributor
Honored ContributorArea of the design
I have designed a CPU and synthesis to FPGA, I can see how mant logical element,register only, Combinational with a register, LUT these information in the compilation report. And I have seen what t...
Altera_ForumHonored Contributor
Honored Contributorvisually? If yes, go to chip planner
