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Altera_Forum's avatar
Altera_Forum
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15 years ago

Area of the design

I have designed a CPU and synthesis to FPGA, I can see how mant logical element,register only, Combinational with a register, LUT these information in the compilation report. And I have seen what t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you for your reply. I have had a simple view of the chip planner. Can it know the exactly size of my design? Since I invetegate the infunence of reducing instruction sets. I want to know the change of area when I reduced the instruction sets. Thank you!