Anyone used the video sync generator in Quartus 7.2??

Hello I tried to use it also, with no success. The doc's are vague about the Avalon-ST interface and how to use is. Do you understand it?

Perhaps we can help each other.

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The reason I ask is that it is confusing me a lot.

The documentation says that the RGB output has a variable width that is configurable via the 'data stream bit width' variable (if no one believes me, it's on page 4 clearly in black and white). I set this to 24 bits and a 'beat per pixel' of 1, just like the example given in the documentation, as this fits my requirements.

The system generated fine in SOPC builder but the symbol in Quartus shows the output having just 8 bits......how can a 24-bit per pixel O/P be sent in an 8-bit wide O/P???? :confused:

I have read over and over the documentation and nothing in it states that the O/P is fixed at 8-bits and Altera support are being useless (3 weeks and no reply)....even though they designed the IP block :mad:

Has anyone else found the same behaviour?

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Did you had any success on using the video sync generator jet?

You can find the altera_avalon_video_sync_generator_hw.tcl file in the

/ip/sopc_builder_ip/altera_avalon_video_sync_generator/ path.

Use some editor to open it, and get into line 103.

Change that 8 to be $data_stream_bit_width

Then you will get the proper result

-Dylan

Yes, I knew that.

That's the file I modified. :)

Since the original ower of this SR (kevin) took some operation these days.

Thus he can't response you. I am sorry for the delay.

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Yes, I knew that.

That's the file I modified. :)

Since the original ower of this SR (kevin) took some operation these days.

Thus he can't response you. I am sorry for the delay.

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Can some one post a zip file with there quartus/sopc project? I still don't get some of the avalon-streaming stuff. Thanks

PS i want to connect a vga/dac chip with will by connected to a VGA screen (640*480).

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I had a response from Altera support, after kicking up a fuss, that there is indeed a bug with the IP block. I have also got a contact within Altera who sent me a modified .tcl script and an alternative vhdl block that will clock in 8 bits per 3 beats and output them in one 24 bit wide O/P. That saved me the effort!

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Can you share the code?I use the video sync generator in my design with DE2-35 and LTM, but the output is a massive noise,like TV.The same design is worked in NEEK, the VD HD DEN signal is fine, but nothing output in EP1C6Q240 or EP2C8Q208, I am frustrated in this.