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I had a response from Altera support, after kicking up a fuss, that there is indeed a bug with the IP block. I have also got a contact within Altera who sent me a modified .tcl script and an alternative vhdl block that will clock in 8 bits per 3 beats and output them in one 24 bit wide O/P. That saved me the effort!
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Can you share the code?I use the video sync generator in my design with DE2-35 and LTM, but the output is a massive noise,like TV.The same design is worked in NEEK, the VD HD DEN signal is fine, but nothing output in EP1C6Q240 or EP2C8Q208, I am frustrated in this.
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