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Altera_Forum's avatar
Altera_Forum
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8 years ago

AM transmitter behaves weird (Cyclone II)

Hello. I tried to make AM transmitter and I got petty wird behavior. This code, which I post here was the only one I got working. Problems start appearing when I change div2(17) or div2(13) to any other numbers than 17 or 13. There should be transmited two frequencies which change once about one second, but when the numbers got changed one of frequencies got noisy or completly disapear, sometime disaper both or there is only the 6,5MHz frequency. I used LEDs insead of antena for easier debugging. What am I doing wrong and can do to make behavior correct. Thank you very much. 

library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity testovaci is
    Port (
        clk :  in std_logic;
        LED :  out std_logic_vector(2 downto 0)                  
);
end testovaci;
architecture Behavioral of testovaci is
    signal div : std_logic_vector(2 downto 0);
    signal div2: std_logic_vector(20 downto 0);
    signal div3: std_logic_vector(26 downto 0);
    signal  count :  std_logic_vector(2 downto 0);
begin 
process (clk) 
begin
    if clk='1' then
        div<=div+1;
        div3<=div3+1;
    end if;
    if div="000" and clk='1' then
        div2<=div2+1;
    end if;
    if div(2)='1' then
            if div3(24)='0' then
                if div2(17)='1' then
                    count <= "111";
                else 
                    count <= "000";
                end if;
            else
                if div2(13)='1' then
                    count <= "111";
                else
                    count <= "000";
                end if;
            end if;
    else 
        count <= "000";
    end if;
end process;
LED(2 downto 0) <=  count(2 downto 0);
end Behavioral;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Restart your design using synchronous (clock edge sensitive) logic. Presently you are implementing weird things like asynchronous counters. They possibly work in a simulation but never in real hardware.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    Restart your design using synchronous (clock edge sensitive) logic. Presently you are implementing weird things like asynchronous counters. They possibly work in a simulation but never in real hardware.

    --- Quote End ---

    Thank you very much. I got it working, but I thought that my code was using synchronous logic (because process is synchronous, right?). I will be happy if you could explain me my mistakes so I don't do them again. Also here is my working code. The only change I did was that I wrapped whole code to "if clk='1' then" block. 

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity testovaci is
    Port (
		clk :  in std_logic; 
		LED :  out std_logic_vector(2 downto 0)                  
);
end testovaci;
architecture Behavioral of testovaci is
	signal div : std_logic_vector(2 downto 0);
	signal div2: std_logic_vector(20 downto 0);
	signal div3: std_logic_vector(26 downto 0);
	signal  count :  std_logic_vector(2 downto 0);
begin 
process (clk) 
begin
	if clk='1' then
		div<=div+1;
		div3<=div3+1;
		if div="000" then
			div2<=div2+1;
		end if;
		if div(2)='1' then
				if div3(24)='0' then
					if div2(14)='1' then
						count <= "111";
					else 
						count <= "000";
					end if;
				else
					if div2(13)='1' then
						count <= "111";
					else
						count <= "000";
					end if;
				end if;
		else 
			count <= "000";
		end if;
	end if;
end process;
LED(2 downto 0) <=  count(2 downto 0);
end Behavioral;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    The below code is counting rising clock edges in a simulation, by working of the sensitivity list. When trying to synthesize it in hardware, the sensitivity list is ignored and it doesn't work as a counter. 

    process (clk) 
begin
  if clk='1' then
    count <= count +1;
  end if;
end process;

    To achieve consistent behavior in functional simulation and synthesis, you need to write 

    process (clk) 
begin
  if rising_edge(clk) then
    count <= count +1;
  end if;
end process;