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Restart your design using synchronous (clock edge sensitive) logic. Presently you are implementing weird things like asynchronous counters. They possibly work in a simulation but never in real hardware.
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Thank you very much. I got it working, but I thought that my code was using synchronous logic (because process is synchronous, right?). I will be happy if you could explain me my mistakes so I don't do them again. Also here is my working code. The only change I did was that I wrapped whole code to "if clk='1' then" block.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity testovaci is
Port (
clk : in std_logic;
LED : out std_logic_vector(2 downto 0)
);
end testovaci;
architecture Behavioral of testovaci is
signal div : std_logic_vector(2 downto 0);
signal div2: std_logic_vector(20 downto 0);
signal div3: std_logic_vector(26 downto 0);
signal count : std_logic_vector(2 downto 0);
begin
process (clk)
begin
if clk='1' then
div<=div+1;
div3<=div3+1;
if div="000" then
div2<=div2+1;
end if;
if div(2)='1' then
if div3(24)='0' then
if div2(14)='1' then
count <= "111";
else
count <= "000";
end if;
else
if div2(13)='1' then
count <= "111";
else
count <= "000";
end if;
end if;
else
count <= "000";
end if;
end if;
end process;
LED(2 downto 0) <= count(2 downto 0);
end Behavioral;
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