Honored ContributorHi,
I'm using a ATLPLL IP In my design. The PLL has one input clock, one areset, one Lock output and one output clock. The input clock is 50MHz . The PLL outputs should be 100MHz. I want the output to be constant 100MHz even if the input frequency will change within the range of at least +/-2MHz. Is it possible? How can I do that? Idan
Honored ContributorNot in general.
Maybe that, if your frequency drift is fast enough and with a zero average value, the bandwidth of the PLL can filter it out. Altera PLL have a programmable bandwidth that you can set to LOW to increase the rejection to input frequency changes. This will affect your lock time however. For a manual: http://www.altera.com/literature/ug/ug_altpll.pdfHonored ContributorHonored ContributorI was saying that, if the input frequency change is fast enough, the PLL can see it has a jitter and maybe able to reject it.
Obvoiusly: 1) if the wandering of input frequency is very slow -> the PLL will follow the input change. 2) it the input frequency cahnge is sudden and with a huge step -> the PLL will lose the lock 3) if the input change of frequency has a non zero average value -> in no way the PLL can guess the right multpiplication factor The only possibility is that the change of input frequency is small in absolute terms, is fast enough to be out of the PLL bandwidth and with a zero average value (the averga is inside the PLL bandwidth). The cahnge of input frequency is then seen as a jitter and filtered by the PLL.Honored ContributorI basically understood your point about a PLL being able to filter jitter. But I think, the ability of the Altera FPGA PLL to perform the same is rather limited, e.g. if you consult the allowable input jitter specification. Furthermore, it seems obvious, that this is not what the original poster intended, see the > 2 MHz variation requirement.
Honored Contributor
