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Honored Contributor
Honored ContributorALTPLL constant output
Hi, I'm using a ATLPLL IP In my design. The PLL has one input clock, one areset, one Lock output and one output clock. The input clock is 50MHz . The PLL outputs should be 100MHz. I want the o...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Maybe that, if your frequency drift is fast enough and with a zero average value, the bandwidth of the PLL can filter it out. --- Quote End --- Sounds very unlikely. Either the PLL is able to track the frequency change or it will loose lock, considering the large frequency range. But you may want to clarify the imagined dynamics of input frequency change. Basically, to keep the output frequency constant for longer than a few usec, the PLL needs a reference frequency. Where should it come from, if the only input signal is unreliable?
