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Honored Contributor
Honored ContributorALTPLL constant output
Hi, I'm using a ATLPLL IP In my design. The PLL has one input clock, one areset, one Lock output and one output clock. The input clock is 50MHz . The PLL outputs should be 100MHz. I want the o...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I want the output to be constant 100MHz even if the input frequency will change within the range of at least +/-2MHz. --- Quote End --- Just being very curious: for what purpose?
